Testimonial : 10

In this time of rapid invention and utilisation of battery-operated products, battery life is a significant problem. Because the traditional Full Adder(FA) uses more energy, we used low power FA circuitry in this study and examined how it functions in lieu of the traditional Full Adder circuitry. Contrary to the latest State of Art, only ten transistors make up the suggested design,which runs on a 0.8 supply voltage. This study compares and contrasts the present design with the FA's suggested work in respect of power and delay. This design consumes low power of only 674.38 nWand is area efficient as it consists of only ten transistors. The presented design of FA consumes less power and offers very less delay of only 2.3 ps than existing designs. TANNER EDA is used to simulate proposed FA and using a 65nm CMOS technology.

Testimonials : 12

Medical image fusion technology and its collective diagnosis are becoming crucial day by day. This task confers the latest algorithm for image fusion of medical images to many diagnostic complications. Firstly, transform is employed on input source images. The result of the application of transform is the decomposition of source images into various subbands. Eminent features are extracted from these subbands by using resnet50. These features are fused by phase congruency and guided filtering fusion rules. Finally, inverse transform gives the original image. The experiment results of this algorithm are compared with different methods by taking some pairs of medical images. Subjective and objective outcomes prove that the proposed algorithm exceeds the current methods by giving optimal performance measures in the area of medical diagnosis. Thus, it is revealed that the suggested multimodal image fusion model provides elevated performance over existing models via diverse diseases using MRI-SPECT and MRI-PET.

Testimonials : 13

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.